ARM Chips List

Last information update: 19th October 1998
Last correction: 3rd August 2000

This document is, like the Acorn Machine List, now frozen and I am not going to be updating it further - beyond correcting any mistakes in the pre-existing information. It is still useful as a historical document about the older ARM chips but I no longer have the time to keep tabs on what ARM is doing and keep this document current.

As of writing this there are currently nine commercially available ARM processor cores with up to ten possibly being available soon. I will seperate the processors into two sections, those currently available and those soon to be available.

Currently available processors

Future processors

ARM Architecture

Currently available processors

Future processors.

ARM Architecture

The ARM Architecture is built around a programmers model of sixteen general purpose registers and a variety of processor modes. Each processor mode offers differing levels of memory access, manipulation of the PC & mode and it's own private registers.

Version 1 - ARM1

By default the programmer 'sees' 16 User mode registers, but when in other modes various registers are swapped out with registers particular to that mode. This table summarises the various modes and registers.

  USR      IRQ      FIQ        SVC
   R10             R10_fiq
   R11             R11_fiq
   R12             R12_fiq
   R13   R13_irq   R13_fiq   R13_svc
   R14   R14_irq   R14_fiq   R14_svc
   R15 (aka PC)
Where a register isn't named in the table, then the USR mode register is visible.

To help keep interupt latency to a minimum FIQ (Fast Interupt Request) mode has a reasonably large set of private registers allowing interupt code to execute in register as much as possible. If there is only one FIQ claimant allowed at a time, a stricture RISC OS stipulates, a further optimisation of pre-loading these registers can be performed.

By convention, and partially enforced by the instruction set, R14 is the 'link' register - commonly holding the return address of any sub routine call. The BL (Branch and Link) instruction automatically stores the correct return address in R14. All registers are general purpose, including R15 which is the Program Counter, status flags and mode register all in one. 26 bits of word aligned address, two bits of processor mode in bits 1 & 0 ( 00 - USR, 01 - IRQ, 10 - FIQ & 11 - SVC) and six bits of processor status (Negative, Carry, oVerflow, Zero, Interupt Request Disable and Fast ).

Instructions include Load/Store (Register, Multiple registers, Byte), Move (and Move NOT), Addition (Add, Add with Carry, Subtract, Subtract with Carry, Reverse Subtract, Reverse Subtract with Carry), Comparison (Compare and Compare Not), Boolean Logic (Test, Test Equivalence, And, Exclusive Or, Or, Bit Clear), Program Flow (Branch, Branch with Link) and the Software Interupt.

Version 2 - ARM2

This architecture added a banked R8 and R9 in FIQ mode, the LDR/STR instruction with register specified shift amounts was withdrawn and two new 'classes' of instruction were added - these being Multiply (multiply and multiply accumulate) and co-processor control (Data operation, co-processor data to ARM register, ARM register to co-processor, Load & Store).

Version 2as - ARM3 & ARM250

Functionaly identical to the v2 architecture this variant added one extra instruction SWP and allocated co-processor zero to be CPU identification and cache control.

Version 3 - ARM6, ARM7 & Amulet 1

This update to the ARM architecture removed the 26bit restriction to the PC counter allowing full 32bit addressing for both data and code. (Previously only data could be addressed across the full 32bit address range.) As a result the dodge of storing processor flags mixed in with the PC in register 15 was no longer possible and a new set of registers were added to hold processor state. For each processor mode the registers CPSR (Current Processor Status Register) and SPSR (Stacked Processor Status Registers) were added. Two new processor modes were added as well Abort32 and Undefined32. For backwards compatibility the chip could be set to emulate the older 26bit mode of operation. A further improvement included the ability to change the byte order of the chip from little-endian to big-endian operation.

All this required the addition of new Move instructions (SPSR to register, CPSR to register, register to SPSR, register to CPSR, immediate constant to SPSR and immediate constant to CPSR.) to communicate with the status registers for each processor mode.

Version 3M

This extension of the version three architecture gave extended Multiply opcodes including unsigned long, unsigned accumulate long, signed long and signed accumlate long multiplys.

Version 4 - StrongARM, ARM8 & ARM9

The new instructions first introduced in the 3M architecture now become part of the main architecture in version 4. Additionally a Halfword (16bit) load/store instruction was added.

Version 5 - ARM10

Some sketchy details are starting to come out about this architecture. But as yet the actual architecture refinements are not available.

Vector Floating Point v1 - ARM10

Developed concurrently with ARM Architecture Version 5 this is a new floating point system giving the ARM family considerably faster floating point performance. As with the Version 5 architecture details are unavailble on exactly what this architecture implements.

Finally for the latest information and details regarding the ARM family of processors why not visit ARMLtd's homepages where details on current and upcoming ARM processors are kept.

Philip R. Banks
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